Timing-Driven Routing for Symmetrical-Array-Based FPGAs yz

Kai Zhu1, Yao-Wen Chang2, and D. F. Wong3 1Triscend Corp., 301 N. Whisman Rd., Mountain View, CA 94043, USA 2Department of Computer and Information Science, National Chiao Tung University, Hsinchu 300, Taiwan 3Department of Computer Sciences, University of Texas at Austin, Austin, Texas 78712, USA Abstract In this paper, we present a timing-driven global router for symmetrical-array-based FPGAs. The routing resources in the symmetrical-array-based FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. Thus, traditional measure of routing delay based on the geometric distance of a signal is not accurate. To consider wirelength and delay simultaneously, we study a model of timing-driven routing trees, arising from the special properties of FPGA routing architectures. We explore the complexity of the routingtree problem and present e cient and e ective approximation algorithms for the problem. Based on the solutions to the routing-tree problem, we present a global-routing algorithm which is able to utilize various routing segments with global consideration to meet the timing constraints. Experimental results on benchmark circuits show that our approach is promising.